Pipelined analog-to-digital converters (ADC's) have become the most popular ADC architecture for sampling rates from a few mega-samples per second (Msps) to over one hundred Msps. Resolutions typically range from eight bits at the faster sample rates up to 16 bits at the lower rates. These resolutions and sampling rates cover a wide range of applications, including CCD imaging, ultrasonic medical imaging, digital receivers, base stations, digital video, cable modems, and fast Ethernet, for example.
With respect to the pipelined ADC architecture, an analog input, VIN, is first sampled and held steady by a sample-and-hold (S&H) (also referred to as track and hold), while an ADC in a first stage coarsely quantizes it to three bits, in some examples. Two and four-bit ADC's are also typical. In the 3-bit example, the 3-bit output of the ADC is then fed to a 3-bit DAC (accurate to the accuracy of the overall converter), and the analog output of the DAC is subtracted from the input and the difference is referred to as “residue.” The subtracted residue is gained up via a residue amplifier (RA) and fed to the next stage (Stage 2) of the pipelined ADC. This gained-up residue continues through the pipeline, providing N bits per stage until it reaches a backend ADC, which resolves the last least significant bits (LSB) bits. Since the bits from each stage are determined at different points in time, all the bits corresponding to the same sample are time-aligned with shift registers before being fed to digital-error-correction logic. When a given stage finishes processing a sample, determining the bits, and passing the residue to the next stage, it can then start processing the next sample received from the sample-and-hold embedded within each stage. This pipelining action is one reason for the high throughput of the ADC.
Most modern pipelined ADCs employ a technique called “digital error correction” to greatly reduce the accuracy requirement of the ADCs (and thus the individual comparators). The DAC's in the pipeline can also affect the overall accuracy of the pipelined ADC. For example, non-linearity in a given DAC can cause inaccuracy in the overall ADC output. The DAC's in the ADC pipeline are often trimmed during manufacturing to account for measured inaccuracies. Unfortunately, as the pipelined ADC is exposed to environmental issues such as temperature, the factory trim parameters may no longer apply.